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Typical Size 6,4 mm X 9,7 mm
TPS54010
SLVS509 - MAY 2004
www.ti.com
2.2 - 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTTM)
FEATURES
* * * * * * * * Separate Low-Voltage Power Bus 8-m MOSFET Switches for High Efficiency at 14-A Continuous Output Adjustable Output Voltage Down to 0.9 V Externally Compensated With 1% Internal Reference Accuracy Fast Transient Response Wide PWM Frequency: Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost
DESCRIPTION
As a member of the SWIFTTM family of dc/dc regulators, the TPS54010 low-input voltage high-output current synchronous buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the VIN input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54010 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPADTM package, which eliminates bulky heatsinks.
APPLICATIONS
* * * Low-Voltage, High-Density Systems With Power Distributed at 2.5 V, 3.3 V Available Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure
SIMPLIFIED SCHEMATIC
2.5 V or 3.3 V 0.68 mH
Input1
350 mF 3.3 V
PVIN
PH TPS54010 BOOT PGND COMP
Output
100 0.047 mF 200 mF 0.1 mF 95 90 120 pF 4.64 kW 3300 pF 422 W 10 kW Efficiency - % 85 80 75 70 65 14.7 kW 1500 pF
EFFICIENCY vs OUTPUT CURRENT
Input2
1 mF
VIN VBIAS
AGND VSENSE
1 mF
Compensation Network
60 55 50 0 2 4 6 8
VIN = 3.3 V, PVIN = 2.5 V, VO = 1.5 V, fs= 700 kHz 10 12 14 16
IO - Output Current - A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2004, Texas Instruments Incorporated
PRODUCT PREVIEW
TPS54010
SLVS509 - MAY 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA -40C to 85C (1) OUTPUT VOLTAGE Adjustible down to 0.9 V PACKAGE Plastic HTSSOP (PWP) (1) PART NUMBER TPS54010PWP
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54010PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
TPA6120A2 SS/ENA, SYNC RT VI Input voltage range VSENSE PVIN, VIN BOOT VO VO Output voltage range Source current VBIAS, COMP, PWRGD PH PH COMP, VBIAS PH IS Sinlk current Voltage differential TJ Tstg Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) COMP SS/ENA, PWRGD AGND to PGND -0.3 V to 7 V -0.3 V to 6 V -0.3 V to 4 V -0.3 V to 4.5 V -0.3 V to 10 V -0.3 V to 7 V -0.6 V to 6 V Internally limited 6 mA 25 A 6 mA 10 mA 0.3 V - 40C to 125C - 65C to 150C 300C
PRODUCT PREVIEW
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN VI TJ Input voltage, VIN Power Input voltage, PVIN Operating junction temperature 3 2.2 -40 2.5 NOM MAX 4 4 125 UNIT V V C
DISSIPATION RATINGS (1) (2)
PACKAGE 28-Pin PWP with solder 28-Pin PWP without solder (1) (2) THERMAL IMPEDANCE JUNCTION-TO-AMBIENT 14.4C/W 27.9C/W TA = 25C POWER RATING 6.94 W (3) 3.58 W TA = 70C POWER RATING 3.81 W 1.97 W TA = 85C POWER RATING 2.77 W 1.43 W
(3) 2
For more information on the PWP package, refer to TI technical brief, literature number SLMA002. Test board conditions: a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch b. 1.5 oz. copper traces located on the top of the PCB c. 1.5 oz. copper ground plane on the bottom of the PCB d. 0.5 oz. copper ground planes on the 2 internal layers e. 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet) Maximum power dissipation may be limited by over current protection.
TPS54010
www.ti.com
SLVS509 - MAY 2004
ELECTRICAL CHARACTERISTICS
TJ = -40C to 125C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)
PARAMETER SUPPLY VOLTAGE, VIN VI Imput voltage, VIN Supply voltage range, PVIN Output = 1.8 V fs = 350 kHz, RT open, PH pin open, PVIN = 2.5 V, SYNC = 0 V VIN fs = 550 kHz, RT open, PH pin open, SYNC 2.5 V, PVIN = 2.5 V SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V IQ Quiescent current fs = 350 kHz, RT open, PH pin open, PVIN = 3.3 V, SYNC = 0 V PVIN fs = 550 kHz, RT open, PH pin open, SYNC 2.5 V, PVIN = 2.5 V, VIN = 3.3 V SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V UNDERVOLTAGE LOCKOUT (VIN) Start threshold voltage, UVLO Stop threshold voltage, UVLO Hysteresis voltage, UVLO Rising and falling edge deglitch, UVLO (1) BIAS VOLTAGE Output voltage, VBIAS Output current, VBIAS (2) CUMULATIVE REFERENCE Vref Accuracy Line regulation (1) (3) Load OSCILLATOR Internally set--free running frequency RT open (1), SYNC 0.8 V RT open (1), SYNC 2.5 V RT = 180 k (1% resistor to AGND) (1) Externally set--free running frequency range RT = 100 k (1% resistor to AGND) RT = 68 k (1% resistor to AGND) (1) High-level threshold voltage, SYNC Low-level threshold voltage, SYNC Pulse duration, SYNC (1) Frequency range, SYNC Ramp Valley (1) Ramp amplitude (peak-to-peak) (1) Minimum controllable on time (1) Maximum duty cycle (1) 90% 50 300 0.75 1 200 700 280 440 262 460 663 2.5 0.8 350 550 280 500 700 420 660 308 540 762 V V ns kHz V V ns kHz kHz regulation (1) (3) 0.882 0.891 0.900 V I(VBIAS) = 0 2.7 2.8 2.9 100 V A 2.7 2.95 2.8 0.16 2.5 3 V 3 2.2 2.5 6.3 8.3 1 4 4 10 13 1.4 V V mA mA mA TEST CONDITIONS MIN TYP MAX UNIT
6
8
mA
6
9
mA
<140
A
V s
REGULATION IL = 7 A, fs = 350 kHz, TJ = 85C IL = 0 A to 14 A, fs = 350 kHz, TJ = 85C 0.07 0.03 %/V %/A
(1) (2) (3)
Specified by design Static resistive loads only Specified by the circuit used in Figure 10
3
PRODUCT PREVIEW
V
TPS54010
SLVS509 - MAY 2004
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ = -40C to 125C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)
PARAMETER ERROR AMPLIFIER Error amplifier open loop voltage gain Error amplifier unity gain bandwidth Error amplifier common mode input voltage range Input bias current, VSENSE Output voltage slew rate (symmetric), COMP PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) SLOW-START/ENABLE Enable threshold voltage, SS/ENA Enable hysteresis voltage, SS/ENA (4) Falling edge deglitch, SS/ENA (4) Internal slow-start time Charge current, SS/ENA SS/ENA = 0 V SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V 2.4 2 1.3 0.82 1.2 0.03 2.5 3.13 5 2 4.1 8 4 1.4 V V s s A mA 10-mV overdrive (4) 70 85 ns 1 k COMP to AGND (4) Parallel 10 k, 160 pF COMP to AGND (4) Powered by internal VSENSE = Vref 1 LDO (4) 90 3 0 60 1.4 110 5 VBIAS 250 dB MHz V nA V/s TEST CONDITIONS MIN TYP MAX UNIT
PRODUCT PREVIEW
Discharge current, SS/ENA POWER GOOD Power good threshold voltage Power good hysteresis voltage (4) Power good falling edge deglitch (4) Output saturation voltage, PWRGD Leakage current, PWRGD CURRENT LIMIT Current limit Current limit leading edge blanking Current limit total response time (4) THERMAL SHUTDOWN Thermal shutdown trip point (4) Thermal shutdown hysteresis (4) OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches time (4)
VSENSE falling
93 3 35
%Vref %Vref s 0.3 1 V A
I(sink) = 2.5 mA VIN = 3.3 V, PVIN = 2.5 V VIN = 3.3 V, PVIN = 2.5 V(1) (4), Output shorted
0.18
14.5
21 100 200
A ns ns C C 20 20
135
150 10
165
VIN = 3 V, PVIN = 2.5 V VIN = 3.6 V, PVIN = 2.5 V
8 8
m
(4)
Specified by design
4
TPS54010
www.ti.com
SLVS509 - MAY 2004
DEVICE INFORMATION
PWP PACKAGE (TOP VIEW)
AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15
RT SYNC SS/ENA VBIAS VIN PVIN PVIN PVIN PVIN PGND PGND PGND PGND PGND
PIN NAME AGND BOOT COMP PGND PH PVIN PWRGD RT SS/ENA SYNC VBIAS VIN VSENSE
PIN NUMBER 1 5 3 15, 16, 17, 18, 19 6-14 20, 21, 22, 23 4 28 26 27 25 24 2
DESCRIPTION Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for details. Bootstrap output. 0.022-F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. Error amplifier output. Connect frequency compensation network from COMP to VSENSE Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the PGND pins close to device package with a high-quality, low-ESR 10-F ceramic capacitor. Power good open drain output. High when VSENSE . 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or the internal shutdown signal is active. Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high-quality, low-ESR 0.1-F to 1.0-F ceramic capacitor. Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package with a high-quality, low-ESR 1-F ceramic capacitor. Error amplifier inverting input. Connect to output voltage compensation network/output divider.
5
PRODUCT PREVIEW
TERMINAL FUNCTIONS
TPS54010
SLVS509 - MAY 2004
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
AGND VIN Enable Comparator Falling Edge Deglitch 2.5 s SHUTDOWN Thermal Shutdown 150C ILIM Comparator Leading Edge Blanking 100 ns VBIAS
VBIAS REG VIN 3.0 - 4.0 V
SS/ENA 1.2 V
PVIN 2.2 - 4.0 V
Hysteresis: 0.03 V VIN UVLO Comparator VIN 2.95 V
Hysteresis: 0.45 V
Falling and Rising Edge Deglitch 2.5 s SS_DIS
BOOT 8 m SHUTDOWN
Internal/External Slow-start (Internal Slow-start Time = 3.35 ms
PH + - Error Amplifier PWM Comparator RQ S Adaptive Dead-Time and Control Logic VIN 8 m OSC Powergood Comparator VSENSE 0.90 Vref PWRGD Falling Edge Deglitch SHUTDOWN 35 s PGND
LOUT CO
VO
PRODUCT PREVIEW
6
Reference VREF = 0.891 V
TPS54010
Hysteresis: 0.03 Vref VSENSE COMP
RT SYNC
TPS54010
www.ti.com
SLVS509 - MAY 2004
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
Drain Source On-State Reststance - m 25 Drain Source On-State Reststance - m VIN = 3.0 V PVIN = 2.5 V IO = 9 A 25 VIN = 3.6 V PVIN = 2.5 V IO = 9 A
DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
f - Internally Set Oscillator Frequency - kHz 750
INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE
20
20
650
15
15
550
TBD
10 5
TBD
10 5
450
350
0 -40
0 25 85 TJ - Junction Temperature - C
125
0 -40
0
25
85
125
250 -40
0
25
85
125
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 1. EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE
f - Externally Set Oscillator Frequency - kHz 800 700 RT = 68 k 600 0.895
Figure 2.
Figure 3.
VOLTAGE REFERENCE vs JUNCTION TEMPERATURE
8 7 V ref - Voltage Reference - V Device Power Losses - W 0.893 6 5 4 3 2 1
DEVICE POWER LOSSES vs LOAD CURRENT
VI = 3.3 V TJ = 125C
0.891
500 RT = 100 k 400 300 RT = 180 k 200 -40
0.889
TBD
0.887
0.885 0 25 85 125 -40 TJ - Junction Temperature - C 0 25 85 TJ - Junction Temperature - C 125
0 0 2 4 6 8 10 12 14 16 IL - Load Current - A
Figure 4. REFERENCE VOLTAGE vs INPUT VOLTAGE
0.895 VO - Output Voltage Regulation - V PVIN = 2.5 V 0.893
140 120 100 Gain - dB 80 60 40 20
Figure 5.
Figure 6. INTERNAL SLOWS-START TIME vs JUNCTION TEMPERATURE
0
ERROR AMPLIFIER OPEN LOOP RESPONSE
3.80 3.65 3.50 3.35 3.20 3.05 2.90 2.75
RL = 10 k, CL = 160 pF, TA = 25C -20 -40 Phase - Degrees -60
VIN = 3.3 V, PVIN = 2.5 V
0.891
Phase
-80 -100 -120
0.889
Gain
-140 -160
0.887
0 -20 1 10 100
-180 -200 1 k 10 k 100 k 1 M 10 M
0.885 3 3.1 3.2 3.3 3.4 VI - Input Voltage - V 3.5 3.6
Internal Slow-Start Time - ms
f - Frequency - Hz
-40
0
25
85
125
TJ - Junction Temperature - C
Figure 7.
Figure 8.
Figure 9.
7
PRODUCT PREVIEW
TPS54010
SLVS509 - MAY 2004
www.ti.com
DETAILED DESCRIPTION
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS54010 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-ms rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin, see the functional block diagram of this data sheet.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-ms falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: 1.2 V t +C d (SS) 5 mA (1) Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: 0.7 V t +C (SS) (SS) 5 mA (2) The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the internal rate.
8
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54010, since it cancels offset errors in the scale and error amplifier circuits.
PRODUCT PREVIEW
OSCILLATOR AND PWM RAMP
The oscillator frequency is set to an internally fixed value of 350 kHz. The oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor between the RT pin to ground. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency + 100 kW 500 [kHz] R (3)
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error amplifier sets the TPS54010 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type-2 or Type-3 compensation can be employed using external compensation components.
TPS54010
www.ti.com
SLVS509 - MAY 2004
PWM CONTROL
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control-logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54010 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped.
The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5- bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents current limit false tripping. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150C. The device is released from shutdown automatically when the junction temperature decreases to 10C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the slow-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence repeats until the fault condition is removed.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or SS/ENA is low. When VIN . UVLO threshold, SS/ENA . enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35-s falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise.
DEAD-TIME CONTROL AMD MOSFET DRIVERS
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.
9
PRODUCT PREVIEW
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